1. Field of the Invention
The present invention generally relates to digital signal pattern generators and, more particularly, to signal pattern generators for stressing memory and logic devices during burn-in.
2. Description of the Prior Art
In recent years, the increased speed and functionality, improved performance and economy of manufacture available from increased integration density in integrated circuits has led to increased numbers of designs of memory and logic circuits. Further, improvements in lithographic techniques and innovations of designs for electronic elements, such as transistors and capacitors, has led to integrated circuit designs which exploit them. At the same time, however, product specifications for integrated circuits have become more stringent and inherent variability of manufacturing processes has increased the need for careful testing of integrated circuit designs and individual devices. At the same time, testing has become far more complex due to the increased numbers of electronic elements contained in an integrated circuit package or module.
Unavoidable manufacturing process variability, in particular, presents substantial difficulty and expense in delivering product having tight tolerances within the product specification. Not only must the product be within specified operational tolerances as manufactured but the manufacturer must assure that the operating tolerances of the product will remain within those tolerances over its useful lifetime. Accordingly, it has become the common practice to provide testing of the individual devices both before and after an extended process called "burn-in" during which the devices are electrically and thermally stressed.
The complexity of integrated circuits at the present state of the art has made exhaustive testing impractical and led to the development of test signal patterns which have an increased likelihood of revealing particular types of defects or decreased operating margins. Even these signal patterns may require substantial periods of time to execute on hardware testers. Since such hardware testers can test only one or a very few devices at a time, throughput is low. Further, the tester must provide signal patterns which are specific to a particular integrated circuit design and programming of a tester for any particular integrated circuit design is difficult and arduous, particularly in development of the testing algorithm and changing the algorithm on the tester when a different design is to be tested.
On the other hand, signal patterns applied to a device for burn-in must be more exhaustive and lengthy to execute but, nevertheless, specific to each design in much the same manner as test patterns but for different reasons. For example, a particular memory design exercising particular groups of memory cells in particular areas of the chip may result in a desired electrical and/or thermal pattern across the chip. Periodic testing is generally included in the burn-in process (although generally at a lower level than the testing described above) so that devices which do not stabilize their operational characteristics within tight tolerances during burn-in can be discarded. Throughput of burn-in apparatus, also referred to as stress systems, is maintained through the fact that the signal patterns can be applied simultaneously to a large number (e.g. several hundreds or thousands) of devices.
Stress systems have become developed into two distinct types intended for use with logic and memory devices, respectively. Each of these two types of stress systems provides a certain degree of hardware economy specific to either logic or memory systems. However, both are difficult to program for a particular integrated circuit device. Further, neither type of stress system can be used with integrated circuit devices other than the type for which the tester is intended.
Specifically, for logic devices, a stress system generally includes a pattern of signals stored in an extensive memory (e.g. vector length (256, 512, etc.).times.1 Megabits to 4 Megabits) which is cycled through in a scanning fashion by counters. In this way, multi-bit signal patterns, sometimes referred to as vectors, are obtained and can be applied to the pins of a logic device. Since the signals are simply combinations of logic bits, any bit in the combination could, in theory, be applied to any pin of the device. However, to achieve the desired burn-in function, the bits of each vector are programmed into memory, generally a static random access memory for high reading rate, in accordance with the pin of the logic device to which it is to be applied. By the same token, there are generally only limited provisions for applying timing related signals (e.g. pulses needed to properly synchronize the logic device) to the device. While the signal patterns can be overwritten by downloading new pattern data into the tester's memory, logic stress testers generally do not have the ability to change the stored patterns dynamically (e.g. "on the fly") during normal operations.
In the case of stress systems adapted for memories, the hardware vector generator must provide both an address and data in a synchronized fashion as well as at least one clock phase. An arithmetic logic unit (ALU) synchronized to a clock phase generally provides an address and data pattern to be applied to the device or module. Since separate address and data vectors and a clock function, which has different signal rise and fall timing compared to the address and data signals, must be provided, each channel (each carrying a respective bit of the address and data vectors or a clock signal) is specific and dedicated to particular pins of the memory, reducing the flexibility of the stress system to accommodate different designs and pin-out arrangements. As with logic testers, programming of the arithmetic logic units is difficult and time-consuming and no provision is generally made for modification of the programmed functions of the ALU's to generate address and data vectors modified from the original vector programming.
It should also be noted in regard to either type of tester or stress system described above that digital circuits may be arranged to operate in response to any of a number of signal waveforms conveying a particular, arbitrary signal pattern. Well-known forms of such signal waveforms are so-called non-return to zero (NRZ), return to zero (RZ), return to one (RO) and return to complement (RC), among others. While it is generally the case that a single digital circuit device will use only one of these waveform conventions and digital signal patterns can be produced in accordance with any of these conventions fairly simply with level shifters, pulse choppers and the like, the number of channels required (e.g. 256, 512, etc.) for testing or stressing current digital circuits requires a substantial amount of circuit hardware to be provided. Further, even in current circuits it could be considered, for example, that clocked circuits responding to a positive or negative transition of a signal require signals according to more than one of these conventions: NRZ for data and RC for the clock in this example. Therefore, it is possible or even likely that new digital circuit designs could exploit use of different signal waveform conventions on different arbitrary pins. Such a facility is not generally provided in known testers or stress systems, even on a basic hardware level and the provision of selectivity of waveforms on a channel-by-channel basis would clearly involve substantial complexity and hardware overhead even to accommodate a relatively few signal waveform conventions. In testers in which such a facility is provided, the facility is obtained at only by a substantial additional level of complexity.
Additionally, modern memory circuits have provided arrangements by which more than one memory access can be achieved in a single memory operational cycle, such as a so-called "write-before-read" function and the like. Additionally a further memory access in a single memory access cycle can be provided by providing a further row and column address through a multiplexer in an operation known as "muxing". Since the muxing operation involves increased numbers of switching operations and digital transistor circuits dissipate heat largely during the transition time of a signal between logic states, electrical and thermal stress can be most readily applied to a memory circuit utilizing the muxing operation. However, known logic stress systems do not generally provide such a facility and, if provided, such muxing is achieved only by the connection of further external hardware pattern generators to the stress system and usually over only a relatively small number of channels.
From the above differences in requirements for driving or exercising each of logic devices and memory devices, it can be readily understood that development of a stress or test system usable with both, particularly where the memory device is embedded within the logic device, would involve substantial hardware unused or other complications engendered when the tester or stress system is applied to either type of device. For example, provision of muxing operations is of substantial complexity even when channels are dedicated to particular device pins but would not generally be used with logic devices. Conversely, in memories where address and data vectors must be separately applied, dedication of pins provides substantial simplification of hardware even allowing for substantial loss of flexibility since assuring that each necessary pin would be driven cannot be otherwise assured within the capabilities of known testers and stress systems. Therefore, the need for different types of testers and stress systems for logic and memory devices as well as different arrangements of testers and stress systems for memories having different pin-out arrangements has required substantial hardware costs in the integrated circuit industry.
Further, known tester and stress systems utilize a fixed sequence of signal patterns which may be repeated. This may or may not be optimal for either testing or burn-in. For example, a binary sequence of signal patterns will develop radically different switching rates and, hence, power dissipation patterns in, for example, an array of switching transistors to which the bits of the pattern are respectively applied. While some hardware arrangements for generating, for example, pseudo-random signal sequences which may statistically provide more equalized average switching rates among transistors, the number of channels necessary in a tester or stress system would make application of such arrangements prohibitively expensive in a tester or stress system capable of exercising modern digital circuits. Further, any such arrangement must also provide for assurance that the sequence of signal patterns provided will be suitably exhaustive for burn-in or to serve the purposes of a particular test sequence.